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Core Configuration
Table 4-2. Status Register Bit Definitions
Bit Number
23–22
Bit Name
CP[1–0]
Reset Value
11
Core Priority
Description
Under control of the CDP[1–0] bits in the OMR, the CP bits specify the
priority of core accesses to external memory. These bits are compared
against the priority bits of the active DMA channel. If the core priority is
greater than the DMA priority, the DMA waits for a free time slot on the
external bus. If the core priority is less than the DMA priority, the core waits
for a free time slot on the external bus. If the core priority equals the DMA
priority, the core and DMA access the external bus in a round robin pattern
(for example, ... P, X, Y, DMA, P, X, Y, ...).
Priority
Mode
Dynamic
Core
Priority
0
DMA
Priority
Determined
OMR
(CDP[1-0])
00
SR (CP[1–0])
00
(Lowest) by DCRn
1
2
3
(DPR[1–0])
for active
DMA
00
00
00
01
10
11
(Highest) channel
Static
core < DMA
core = DMA
core > DMA
01
10
11
xx
xx
xx
21
RM
0
Rounding Mode
Selects the type of rounding performed by the Data ALU during arithmetic
operations. If RM is cleared, convergent rounding is selected. If RM is set,
two’s-complement rounding is selected.
20
SM
0
Arithmetic Saturation Mode
Selects automatic saturation on 48 bits for the results going to the
accumulator. This saturation is performed by a special circuit inside the
MAC unit. The purpose of this bit is to provide an Arithmetic Saturation
mode for algorithms that do not recognize or cannot take advantage of the
extension accumulator.
19
CE
0
Cache Enable
Enables/disables the instruction cache controller. If CE is set, the cache is
enabled, and instructions are cached into and fetched from the internal
Program RAM. If CE is cleared, the cache is disabled and the DSP56300
core fetches instructions from external or internal program memory,
according to the memory space table of the specific DSP56300 core-based
device.
Note:
To ensure proper operation, do not clear Cache Enable mode
while Burst mode is enabled (OMR[BE] is set).
18
0
Reserved. Write to zero for future compatibility.
17
SA
0
Sixteen-Bit Arithmetic Mode
Affects data width functionality, enabling the Sixteen-bit Arithmetic mode of
operation. When SA is set, the core uses 16-bit operations instead of 24-bit
operations. In this mode, 16-bit data is right-aligned in the 24-bit memory
locations, registers, and 24-bit register portions. Shifting, limiting, rounding,
arithmetic instructions, and moves are performed accordingly. For details
on Sixteen-Bit Arithmetic mode, consult the DSP56300 Family Manual.
DSP56311 User’s Manual, Rev. 2
4-6
Freescale Semiconductor
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